View M24256-BF_5027352.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M24256-BF M24256-BR M24256-BW M24256-DR
256 Kbit serial IC bus EEPROM with three Chip Enable lines
Features

256 Kbit EEPROM addressed through the I2C bus Supports the I2C bus modes: - 1 MHz Fast-mode Plus - 400 kHz Fast mode - 100 kHz Standard mode Supply voltage ranges: - 1.7 V to 5.5 V - 1.8 V to 5.5 V - 2.5 V to 5.5 V Write Control input Byte and Page Write Random and sequential read modes Self-timed programming cycle Automatic address incrementing Enhanced ESD/latch-up protection More than 1 000 000 write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant) TSSOP8 (DW) SO8 (MN) 150 mils width
SO8 (MW) 208 mils width

WLCSP (CS)
UFDFPN8 (MB) 2 x 3 mm (MLP)
March 2010
Doc ID 6757 Rev 21
1/42
www.st.com 1
Contents
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 2.6.2 2.6.3 2.6.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Identification Page Write (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . 17 Lock Identification Page (M24256-DR only) . . . . . . . . . . . . . . . . . . . . . . . 17 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20 Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Contents
3.18 3.19
Read Identification Page status (locked/unlocked) . . . . . . . . . . . . . . . . . . 22 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4 5 6 7 8 9
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 6757 Rev 21
3/42
List of tables
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code (for memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device select code to access the Identification page (M24256-DR only) . . . . . . . . . . . . . . 11 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO8W - 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 31 SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 32 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WLCSP 0.5 mm pitch, package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Available M24256-DR products (package, voltage range, temperature grade) . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO8W - 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 31 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 32 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 6757 Rev 21
5/42
Description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
1
Description
The M24256-Bx devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 32 Kb x 8 bits. The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance with the I2C bus definition. The M24256-DR also decodes the type identifier code (1011) when accessing the identification page. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. Figure 1. Logic diagram
Table 1.
Signal names
Signal name Function Chip Enable Serial Data Serial Clock Write Control Supply voltage Ground Inputs I/O Input Input Direction
E0, E1, E2 SDA SCL WC VCC VSS
6/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 2. Package connections
Description
E0 E1 E2 VSS
1 2 3 4
8 7 6 5
VCC WC SCL SDA
AI04035e
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
VCC E0 WC SDA SCL
E1
E2
VSS
ai14712
Doc ID 6757 Rev 21
7/42
Signal description
M24256-BF, M24256-BR, M24256-BW, M24256-DR
2
2.1
Signal description
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR'ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code. When not connected (left floating), these inputs are read as Low (0,0,0). Figure 4. Device select code
VCC VCC
M24xxx Ei
M24xxx Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven High, device select and address bytes are acknowledged, Data bytes are not acknowledged.
8/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Signal description
2.5
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
2.6.1
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
VCC has to rise continuously from 0 V up to VCC(min) (see Table 8, Table 9 and Table 10), and the rise time must not vary faster than 1 V/s.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches an internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage defined in Table 8, Table 9 and Table 10. When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. However, the device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power on reset threshold voltage, the device stops responding to any instruction sent to it.
2.6.4
Power-down conditions
During power-down (where VCC decreases continuously), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal Write cycle in progress).
Doc ID 6757 Rev 21
9/42
Signal description Figure 5.
M24256-BF, M24256-BR, M24256-BW, M24256-DR I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus)
Bus line pull-up resistor (k )
100
When tLOW = 1.3 s (min value for fC = 400 kHz), the Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left.
VCC
10
4 k
R bu sx C bu s= Here Rbus x Cbus = 120 ns 40
Rbus
0n s
IC bus master
SCL SDA
M24xxx
1 10
30 pF
100 Bus line capacitor (pF)
1000
Cbus
ai14796b
Figure 6.
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus)
VCC
When tLOW = 700 ns (max possible value for fC = 1 MHz), the Rbus x Cbus time constant must be below the 270 ns time constant line represented on the left. When tLOW = 400 ns (min value for fC = 1 MHz), the Rbus x Cbus time constant must be below the 100 ns time constant line represented on the left.
Bus line pull-up resistor (k )
100
R
bus x C bus = 270
Rbus IC bus master SCL SDA Cbus
ns
10 5
R
bus x C bus = 10
M24xxx
0 ns
Here, Rbus x Cbus = 150 ns
1 10 30 Bus line capacitor (pF)
ai14795d
100
10/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 7. I2C bus protocol
Signal description
SCL
SDA SDA Input SDA Change
Start condition
Stop condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
Start condition
SCL
1
2
3
7
8
9
SDA
MSB
ACK
Stop condition
AI00792c
Table 2.
Device select code (for memory array)
Device type identifier(1) b7 b6 0 b5 1 b4 0 Chip Enable address(2) b3 E2 b2 E1 b1 E0 RW b0 RW
Device select code
1
1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
Device select code to access the Identification page (M24256-DR only)
Device type identifier(1) b7 b6 0 b5 1 b4 1 Chip Enable address(2) b3 E2 b2 E1 b1 E0 RW b0 RW
Device select code
1
1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Doc ID 6757 Rev 21
11/42
Signal description Table 4.
b15
M24256-BF, M24256-BR, M24256-BW, M24256-DR Most significant address byte
b14 b13 b12 b11 b10 b9 b8
Table 5.
b7
Least significant address byte
b6 b5 b4 b3 b2 b1 b0
12/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3
Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always slave in all communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low.
Doc ID 6757 Rev 21
13/42
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.5
Addressing the memory array
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable "Address" (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 6.
Mode Current Address Read Random Address Read Sequential Read Byte Write Page Write
1. X = VIH or VIL.
Operating modes
RW bit 1 0 1 1 0 0 WC(1) X X 1 X X VIL VIL 1 1 64 re-Start, device select, RW = 1 Similar to Current or Random Address Read Start, device select, RW = 0 Start, device select, RW = 0 Bytes 1 Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, Address
14/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 8.
WC ACK Byte Write
Start
Device operation
Write mode sequences with WC = 1 (data write inhibited)
ACK Byte addr Byte addr
ACK Data in
NO ACK
Dev sel R/W
WC ACK Page Write
Start
ACK Byte addr Byte addr
ACK
NO ACK Data in 1 Data in 2
Dev sel R/W
WC (cont'd) NO ACK Page Write (cont'd) NO ACK
Data in N
Stop
Stop
AI01120d
Doc ID 6757 Rev 21
15/42
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High. Any Write instruction with Write Control (WC) driven High (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 8. Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (Table 4) is sent first, followed by the least significant byte (Table 5). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device's internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests.
3.7
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven High, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9.
3.8
Page Write (memory array)
The Page Write mode allows up to 64 bytes to be written in a single Write cycle, provided that they are all located in the same `row' in the memory: that is, the most significant memory address bits (b15-b6) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 64 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (the 7 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition.
16/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.9
Identification Page Write (M24256-DR only)
The Identification page is written by issuing an ID Write instruction. This instruction uses the same protocol and format as the Page Write in memory array, except for the following differences:

Device Type Identifier = 1011b MSB address bits A15/A6 are don't care except for address bit A10 which must be `0'. LSB address bits A5/A0 define the byte address inside the identification page.
If the Identification page is locked, the data bytes transferred during the Identification Page Write instruction are not acknowledged (NoAck).
3.10
Lock Identification Page (M24256-DR only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:

Device Type Identifier = 1011b Address bit A10 must be `1'; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care.
If the Identification Page is locked, the data bytes transferred during the ID Write instruction are not acknowledged (NoAck).
3.11
ECC (error correction code) and write cycling
The M24256-Bx and M24256-DRdevices offer an ECC (error correction code) logic which compares each 4-byte word with its six associated ECC EEPROM bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes making up the word. It is therefore recommended to write by word (4 bytes) in order to benefit from the larger amount of Write cycles. The M24256-Bx and M24256-DR devices are qualified at 1 million (1 000 000) Write cycles, using a cycling routine that writes to the device by multiples of 4-bytes.
Doc ID 6757 Rev 21
17/42
Device operation Figure 9.
WC ACK Byte Write Dev sel
M24256-BF, M24256-BR, M24256-BW, M24256-DR Write mode sequences with WC = 0 (data write enabled)
ACK Byte addr Byte addr
ACK Data in
ACK
Start
R/W
WC ACK Page Write Dev sel Byte addr R/W ACK Byte addr ACK Data in 1 ACK Data in 2
WC (cont'd)
Start
ACK Page Write (cont'd) Data in N
ACK
Stop
Stop
AI01106d
18/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 10. Write cycle polling flowchart using ACK
Write cycle in progress
Device operation
Start condition Device select with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next operation is addressing the memory
YES
ReStart
Send Address and Receive ACK
Stop
NO
Start condition
YES
Data for the Write operation
Device select with RW = 1
Continue the Write operation
Continue the Random Read operation
AI01847d
3.12
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 16, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10, is:

Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 6757 Rev 21
19/42
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.13
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device's internal address counter is incremented by one, to point to the next byte address. Figure 11. Read mode sequences
ACK Current Address Read
Start
NO ACK Data out
Dev sel R/W
ACK Random Address Read
Start
ACK Byte addr Byte addr
Stop
ACK Dev sel *
Start
ACK Data out R/W
NO ACK
Dev sel * R/W
ACK Sequential Current Read
Start
ACK Data out 1
ACK
NO ACK Data out N
Stop
Dev sel R/W
ACK Sequential Random Read
Start
ACK Byte addr Byte addr
ACK Dev sel *
Start
ACK Data out 1 R/W
ACK
Dev sel * R/W
ACK
NO ACK Data out N
Stop
AI01105d
3.14
Random Address Read (in memory array)
A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
20/42
Doc ID 6757 Rev 21
Stop
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Device operation
3.15
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11, without acknowledging the byte.
3.16
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 11. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h.
3.17
Read Identification Page
This instruction uses the same protocol and format as the Random Address Read (in memory array) instruction. The only differences between the two instructions are that, in the Read Identification Page instruction:

the device type identifier = 1011b MSB address bits A15/A6 are don't care except for address bit A10 which must be `0'. LSB address bits A5/A0 define the byte address inside the identification page. During a Read Identification Page instruction, the (A5/A0) address should not exceed 3Fh.
Doc ID 6757 Rev 21
21/42
Device operation
M24256-BF, M24256-BR, M24256-BW, M24256-DR
3.18
Read Identification Page status (locked/unlocked)
The locked/unlocked status of the Identification page can be checked by issuing a specific truncated instruction consisting of the Identification Page Write instruction followed by one data byte. The data byte will be acknowledged if the Identification page is unlocked, while it will not be acknowledged if the Identification page is locked. Once the acknowledge bit of this data byte is read, it is recommended to generate a Start condition followed by a Stop condition, so that:

The instruction is truncated and not executed as the Start condition resets the device internal logic. The device is set to Standby mode by the Stop condition.
3.19
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode.
22/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Initial delivery state
4
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7.
Symbol TA TSTG TLEAD VIO VCC IOL VESD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Input or output range Supply voltage DC output current (SDA = 0) Electrostatic discharge voltage (human body model)
(2)
Min. -40 -65 See -0.50 -0.50
Max. 130 150 note (1) 6.5 6.5 5
Unit C C C V V mA V
-3000
3000
ECOPACK(R)
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST 7191395 specification, and the European directive on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS) 2002/95/EC.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )
Doc ID 6757 Rev 21
23/42
DC and AC parameters
M24256-BF, M24256-BR, M24256-BW, M24256-DR
6
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3)
Operating conditions (voltage range W)
Parameter Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 9.
Symbol VCC TA
Operating conditions (voltage range R)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 10.
Symbol VCC TA
Operating conditions (voltage range F)
Parameter Supply voltage Ambient operating temperature Min. 1.7 -40 Max. 5.5 85 Unit V C
Table 11.
Symbol CL
AC test measurement conditions
Parameter Load capacitance Input rise and fall times Input levels Input and output timing reference levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
Figure 12. AC test measurement I/O waveform
Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
24/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 12.
Symbol CIN CIN ZL(2) ZH(2)
DC and AC parameters
Input parameters
Parameter(1) Input capacitance (SDA) Input capacitance (other pins) Input impedance (E2, E1, E0, WC) Input impedance (E2, E1, E0, WC) VIN < 0.3VCC VIN > 0.7VCC 30 500 Test condition Min. Max. 8 6 Unit pF pF k k
1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 13.
Symbol
DC characteristics (voltage range W)
Parameter Test conditions (see Table 8 and Table 11) VIN = VSS or VCC device in Standby mode SDA in Hi-Z, external voltage applied on SDA: VSS or VCC VCC = 2.5 V, fc = 400 kHz (rise/fall time < 50 ns) Min. Max. Unit
ILI
Input leakage current (SCL, SDA, E0, E1, E2) Output leakage current
2
A
ILO
2 1 2 5(1) 5
A mA mA mA A
ICC
Supply current (Read) VCC = 5.5 V, fc = 400 kHz (rise/fall time < 50 ns) Supply current (Write) During tW, 2.5 V < VCC < 5.5 V Standby supply current Device grade 3 Device not selected VIN = VSS or VCC, VCC Device grade 6 = 2.5 V VIN = VSS or VCC, VCC = 5.5 V
(2),
ICC0
ICC1
2 5 -0.45 0.7VCC 0.3VCC 6.5 V A V
VIL
Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA)
VIH
Input high voltage (WC, E0, E1, E2) Output low voltage IOL = 2.1 mA, VCC = 2.5 V
0.7VCC VCC+0.6 0.4 V
VOL
1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 21
25/42
DC and AC parameters Table 14.
Symbol
M24256-BF, M24256-BR, M24256-BW, M24256-DR DC characteristics (voltage range R)
Parameter Test conditions (in addition to those in Table 9) VIN = VSS or VCC device in Standby mode SDA in Hi-Z, external voltage applied on SDA: VSS or VCC VCC = 1.8 V, fc= 400 kHz (rise/fall time < 50 ns) VCC = 2.5 V, fc= 400 kHz (rise/fall time < 50 ns) Min. Max. Unit
ILI ILO
Input leakage current (E1, E2, SCL, SDA) Output leakage current
2 2 0.8 1 2 2.5 5(2) 1 2 3 -0.45 -0.45 0.75VCC 0.7VCC 0.75VCC 0.7VCC 0.25 VCC 0.3 VCC 6.5
A A mA mA mA mA mA A A A V
ICC
Supply current (Read) VCC = 5.0 V, fc= 400 kHz (rise/fall time < 50 ns) 1.8 V < VCC < 5.5 V, fc= 1 MHz(1) (rise/fall time < 50 ns)
ICC0
Supply current (Write)
During tW, 1.8 V < VCC < 5.5 V Device not VIN = VSS or VCC, VCC = 1.8 V selected(3),
ICC1
Standby supply current
Device not selected(3), VIN = VSS or VCC, VCC = 2.5 V Device not selected(3), VIN = VSS or VCC, VCC = 5.5 V
VIL
Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA)
1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V 1.8 V VCC < 2.5 V 2.5 V VCC < 5.5 V 1.8 V VCC < 2.5 V 2.5 V VCC 5.5 V IOL = 1 mA, VCC = 1.8 V
V 6.5 VCC+0.6 VCC+0.6 0.2 0.4 0.4 V V V V
VIH Input high voltage (WC, E0, E1, E2)
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V IOL = 3.0 mA, VCC = 5.5 V
1. Only for devices operating at fC max = 1 MHz (see Table 17). 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
26/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 15.
Symbol
DC and AC parameters
DC characteristics (voltage range F)(1)
Parameter Input leakage current (E1, E2, SCL, SDA) Output leakage current Test condition (in addition to those in Table 9) VIN = VSS or VCC device in Standby mode SDA in Hi-Z, external voltage applied on SDA: VSS or VCC VCC = 1.7 V, fc= 400 kHz (rise/fall time < 50 ns) Min. Max. Unit
ILI ILO
2 2 0.8 1 2 5(2) 1 2 3 -0.45 -0.45 0.75VCC 0.7VCC 0.75VCC 0.7VCC 0.25 VCC 0.3 VCC 6.5
A A mA mA mA mA A A A
ICC
Supply current (Read)
VCC = 2.5 V, fc= 400 kHz (rise/fall time < 50 ns) VCC = 5.0 V, fc= 400 kHz (rise/fall time < 50 ns)
ICC0
Supply current (Write)
During tW, 1.7 V < VCC < 5.5 V Device not VIN = VSS or VCC, VCC = 1.7 V selected(3),
ICC1
Standby supply current
Device not selected(3), VIN = VSS or VCC, VCC = 2.5 V Device not selected(3), VIN = VSS or VCC, VCC = 5.5 V
VIL
Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA)
1.7 V VCC < 2.5 V 2.5 V VCC 5.5 V 1.7 V VCC < 2.5 V 2.5 V VCC 5.5 V 1.7 V VCC < 2.5 V 2.5 V VCC 5.5 V IOL = 1 mA, VCC = 1.7 V
V
V 6.5 VCC+0.6 VCC+0.6 0.2 0.4 0.4 V V V V
VIH Input high voltage (WC, E0, E1, E2)
VOL
Output low voltage
IOL = 2.1 mA, VCC = 2.5 V IOL = 3.0 mA, VCC = 5.5 V
1. Preliminary data. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 6757 Rev 21
27/42
DC and AC parameters Table 16.
M24256-BF, M24256-BR, M24256-BW, M24256-DR 400 kHz AC characteristics
Test conditions specified in Table 8, Table 9, Table 10 and Table 11
Symbol fC tCHCL tCLCH tQL1QL2
(2)
Alt. fSCL tHIGH tLOW tF tR tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Clock frequency
Parameter
Min.(1)
Max.(1) 400
Unit kHz ns ns
Clock pulse width high Clock pulse width low SDA (out) fall time Input signal rise time Input signal fall time Data in set up time Data in hold time Data out hold time Clock low to next data valid (access time) Start condition setup time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition Write time Pulse width ignored (input filter on SCL and SDA) - single glitch
600 1300 20
(3)
120
(4) (4)
ns ns ns ns ns ns
tXH1XH2 tXL1XL2 tDXCX tCLDX tCLQX tCLQV(6)(7) tCHDL tDLCL tCHDH tDHDL tW tNS
(4) (4)
100 0 100(5) 100(5) 600 600 600 1300 5 80(8) 900
ns ns ns ns ns ms ns
1. All values are referred to VIL(max) and VIH(min). 2. Characterized only, not tested in production. 3. With CL = 10 pF. 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 5. The new M24xxx-W, M24xxx-R, and M24xxx-BF devices (identified by the process letter K) offer tCLQX = 100 ns (min) and tCLQV = 100 ns (min), while the current devices (process letter A) offer tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a safe margin compared to the I2C specification which recommends tCLQV = 0 ns (min). 6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus x Cbus time constant is within the values specified in Figure 6. 8. The current M24xxx devices (identified by the Process letter A) offer tNS=100 ns (min), the new M24256BR and M24256-DR device (identified by the process letter K) offer tNS=80 ns (min). Both products offer a safe margin compared to the 50 ns minimum value recommended by the I2C specification.
28/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 17. 1 MHz AC characteristics(1)
DC and AC parameters
Test conditions specified in Table 9 and Table 11 Symbol fC tCHCL tCLCH tXH1XH2 tXL1XL2 tQL1QL2 tDXCX tCLDX tCLQX tCLQV(7)(8) tCHDL tDLCL tCHDH tDHDL tW tNS(4)
(4)
Alt. fSCL tHIGH tLOW tR tF tF tSU:DAT Clock frequency
Parameter 0
Min.(2)
Max.(2) 1 (3) (3)
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time Data in setup time
300 400
(3) (3)
20 80 0
(5)
120 500 5 50(9)
tHD:DAT Data in hold time tDH tAA tSU:STA tHD:STA tSU:STO tBUF tWR Data out hold time Clock low to next data valid (access time) Start condition setup time Start condition hold time Stop condition setup time Time between Stop condition and next Start condition Write time
50(6) 50(6) 250 250 250 500 -
Pulse width ignored (input filter on SCL and SDA)
1. Only new M24256-BR and M24256-DR devices identified by the process letter K are qualified at 1 MHz. 2. All values are referred to VIL(max) and VIH(min). 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the IC specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz, or less than 120 ns when fC < 1 MHz. 4. Characterized only, not tested in production. 5. With CL = 10 pF. 6. The new M24xxx devices (identified by the process letter K) offer tCLQX=100 ns (min) and tCLQV=100 ns (min) which is an improved value compared to the tCLQX=50 ns (min) and tCLQV=50 ns (min) offered by the current M24xxx devices (identified with the Process letter A) 7. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 8. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that the Rbus x Cbus time constant is within the values specified in Figure 6. 9. The new M24xxx devices (identified with the process letter K) offer tNS = 80 ns (min) which is an improved value compared to the current M24xxx devices (identified by the process letter A).
Doc ID 6757 Rev 21
29/42
DC and AC parameters Figure 13. AC waveforms
tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDL Start condition tXH1XH2 SDA Input tCLDX tCHCL
M24256-BF, M24256-BR, M24256-BW, M24256-DR
tCLCH
tXL1XL2
SDA tDXCH Change
tCHDH tDHDL Start Stop condition condition
SCL
SDA In tW tCHDH Stop condition Write cycle tCHDL Start condition
tCHCL SCL tCLQV SDA Out Data valid tCLQX Data valid
AI00795e
tQL1QL2
30/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
7
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 14. SO8W - 8-lead plastic small outline, 208 mils body width, package outline
A2 b e D
A c CP
N
E E1
1
A1
k
L
6L_ME
1. Drawing is not to scale.
Table 18.
SO8W - 8-lead plastic small outline, 208 mils body width, package data
millimeters inches(1) Max 2.5 0 1.51 0.4 0.2 0.35 0.1 0.25 2 0.51 0.35 0.1 6.05 5.02 7.62 1.27 0 0.5 8 6.22 8.89 10 0.8 0.05 0.1976 0.3 0 0.0197 8 0.0157 0.0079 0 0.0594 0.0138 0.0039 Typ Min Max 0.0984 0.0098 0.0787 0.0201 0.0138 0.0039 0.2382 0.2449 0.35 10 0.0315
Symbol Typ A A1 A2 b c CP D E E1 e k L N (number of pins) Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 6757 Rev 21
31/42
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 15. SO8N - 8-lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 19.
SO8N - 8-lead plastic small outline, 150 mils body width, package mechanical data
millimeters inches(1) Max 1.75 0.1 1.25 0.28 0.17 0.48 0.23 0.1 4.9 6 3.9 1.27 4.8 5.8 3.8 0.25 0 0.4 1.04 5 6.2 4 0.5 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ Min Max 0.0689 0.0098
Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min
1. Values in inches are converted from mm and rounded to 4 decimal digits.
32/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Package mechanical data
Figure 16. TSSOP8 - 8-lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 20.
Symbol
TSSOP8 - 8-lead thin shrink small outline, package mechanical data
millimeters Typ Min Max 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0 8 8 2.900 - 6.200 4.300 0.450 3.100 - 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0 8 8 0.1142 - 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ inches(1) Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 - 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1 N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Doc ID 6757 Rev 21
33/42
Package mechanical data
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3. The circle in the top view of the package indicates the position of pin 1.
Table 21.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data
millimeters inches(1) Max 0.6 0.05 0.3 2.1 1.7 3.1 0.3 0.5 0.15 0.3 0.08 0.0118 0.08 Typ 0.0217 0.0008 0.0098 0.0787 0.063 0.1181 0.0079 0.0197 0.0177 Min 0.0177 0 0.0079 0.0748 0.0591 0.1142 0.0039 0.0157 Max 0.0236 0.002 0.0118 0.0827 0.0669 0.122 0.0118 0.0197 0.0059
Symbol Typ A A1 b D D2 E E2 e L L1 L3 ddd
(2)
Min 0.45 0 0.2 1.9 1.5 2.9 0.1 0.4
0.55 0.02 0.25 2 1.6 3 0.2 0.5 0.45
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
34/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 18. WLCSP, 0.5 mm pitch, package outline
Package mechanical data
Orientation reference 3 D 2 1
e2 e E G B
A B C D E
F
e3 e1 A2 A1 A
1. Drawing is not to scale.
Table 22.
Symbol
WLCSP 0.5 mm pitch, package mechanical data(1)
Millimeters Inches(2) Max 0.65 0.27 0.380 Typ 0.0236 0.0096 0.0140 Min 0.0217 0.0087 0.0130 O 0.0122 1.99 1.805 0.0776 0.0703 0.0197 0.0341 0.0098 0.0170 0.502 0.342 8 0.602 0.442 0.0217 0.0154 0.0198 0.0135 8 0.0237 0.0174 0.0768 0.0695 0.0783 0.0711 Max 0.0256 0.0106 0.0150
Typ
A A1 A2 B D E e e1 e2 e3 F G N
(3)
Min
0.55 0.22 0.330 O 0.311
0.60 0.245 0.355
1.97 1.785 0.5 0.866 0.25 0.433 0.552 0.392
1.95 1.765
1. Preliminary data. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 3. N is the total number of terminals.
Doc ID 6757 Rev 21
35/42
Part numbering
M24256-BF, M24256-BR, M24256-BW, M24256-DR
8
Table 23.
Example:
Part numbering
Ordering information scheme
M24256-B W MW 6 T P /AB
Device type M24 = I2C serial access EEPROM Device function 256- = 256 Kbit (32 Kb x 8) Device family B: Without Identification page D: With additional Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package MW = SO8 (208 mils width) MN = SO8 (150 mils body width) DW = TSSOP8 MB = UFDFPN8 (MLP8) CS = WLCSP Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Automotive: device tested with high reliability certified flow(1) over -40 to 125 C Option blank = standard packing T = tape and reel packing Plating technology P or G = ECOPACK(R) (RoHS compliant) Process /A = F8L process /AB = F8L process (for device grade 3) /K = F8H process
1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.
36/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24.
Part numbering
Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade)
M24256-BW 2.5 V to 5.5 V Range 6, Range 3 Range 6 Range 6 M24256-BR 1.8 V to 5.5 V Range 6 Range 6 Range 6 M24256-BF 1.7 V to 5.5 V Range 6 Range 6
Package SO8N (MN) SO8W (MW) TSSOP (DW) WLCSP (CS) UFDFPN8 (MB)
Table 25.
Available M24256-DR products (package, voltage range, temperature grade)
Package M24256-DR 1.8 V to 5.5 V Range 6 Range 6
SO8N (MN) TSSOP (DW)
Doc ID 6757 Rev 21
37/42
Revision history
M24256-BF, M24256-BR, M24256-BW, M24256-DR
9
Revision history
Table 26.
Date
Document revision history
Revision Changes Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated LGA8 and SO8(wide) packages added References to PSDIP8 changed to PDIP8, and Package Mechanical data updated LGA8 Package Mechanical data and illustration updated SO16 package removed LGA8 Package given the designator "LA" LGA8 Package mechanical data updated Document becomes Preliminary Data Test conditions for ILI, ILO, ZL and ZH made more precise VIL and VIH values unified. tNS value changed Document promoted to Full Datasheet Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5 removed. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified. AEC-Q100-002 compliance. VIL specification unified for SDA, SCL and WC Initial delivery state is FFh (not necessarily the same as Erased). LGA package removed, TSSOP8 and SO8N packages added (see Package mechanical data section and Table 23: Ordering information scheme). Voltage range R (1.8V to 5.5V) also offered. Minor wording changes. ZL Test Conditions modified in Table 12: Input parameters and Note 2 added. ICC and ICC1 values for VCC = 5.5V added to Table 13: DC characteristics (voltage range W). Note added to Table 13: DC characteristics (voltage range W). Power On Reset paragraph specified. tW max value modified in Table 16: 400 kHz AC characteristics and note 4 added. Plating technology changed in Table 23: Ordering information scheme. Resistance and capacitance renamed in Figure 6.
29-Jan-2001
1.1
10-Apr-2001 16-Jul-2001 02-Oct-2001 13-Dec-2001 12-Jun-2001 22-Oct-2003
1.2 1.3 1.4 1.5 1.6 2.0
02-Sep-2004
3.0
22-Feb-2005
4.0
38/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 26.
Date
Revision history
Document revision history (continued)
Revision Changes Power On Reset paragraph replaced by Section 2.6: Supply voltage (VCC). Figure 4: Device select code added. ECC (error correction code) and write cycling added and specified at 1 Million cycles. ICC0 added and ICC1 specified over the whole voltage range in Table 13 and Table 14. PDIP8 package removed. Packages are ECOPACK(R) compliant. Small text changes. M24256-BW and M24256-BR part numbers added. Section 3.11: ECC (error correction code) and write cycling updated. ICC and ICC1 modified in Table 14: DC characteristics (voltage range R). tW modified in Table 16: 400 kHz AC characteristics. SO8Narrow package specifications updated (see Table 19 and Figure 15). Blank option removed from below Plating technology in Table 23: Ordering information scheme. Section 2.6: Supply voltage (VCC) modified. Section 3.11: ECC (error correction code) and write cycling modified. JEDEC standard and European directive references corrected below Table 7: Absolute maximum ratings. Rise/fall time conditions modified for ICC and VIH max modified in Table 13: DC characteristics (voltage range W) and Table 14: DC characteristics (voltage range R) Note 1 removed from Table 13: DC characteristics (voltage range W). SO8W package specifications modified in Section 7: Package mechanical data. Table 24: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) and Table 26: Available M24512-x products (package, voltage range, temperature grade) added. Section 2.5: VSS ground added. Small text changes. VIO max changed and Note 1 updated to latest standard revision in Table 7: Absolute maximum ratings. Note removed from Table 12: Input parameters. VIH min and VIL max modified in Table 14: DC characteristics (voltage range R). Removed tCH1CH2, tCL1CL2 and tDH1DH2, and added tXL1XL2, tDL1DL2 and Note 3 in Table 16: 400 kHz AC characteristics. tXH1XH2, tXL1XL2 and Note 2 added to Table 17: 1 MHz AC characteristics. Figure 13: AC waveforms modified. Package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see Section 7: Package mechanical data).
05-May-2006
5
16-Oct-2006
6
02-Jul-2007
7
16-Oct-2007
8
Doc ID 6757 Rev 21
39/42
Revision history Table 26.
Date
M24256-BF, M24256-BR, M24256-BW, M24256-DR Document revision history (continued)
Revision Changes 1 MHz frequency introduced (M24512-HR root part number). Section 2.6.3: Device reset modified. Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) modified, Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) added. tNS moved from Table 12 to Table 16. ILO test conditions modified in Table 13. Table 14: DC characteristics (voltage range R) and Table 17: 1 MHz AC characteristics modified. Small text changes. Small text changes. M24256-BHR root part number added. Section 2.6.3: Device reset on page 9 updated. Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) on page 10 updated. Caution removed in Section 3.11: ECC (error correction code) and write cycling. M24512-W and M24256-BW offered in the device grade 3 option (automotive temperature range): - Table 8: Operating conditions (voltage range W), - Table 13: DC characteristics (voltage range W), - /AB Process letters added to Table 23: Ordering information scheme, - Table 24: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) and - Table 26: Available M24512-x products (package, voltage range, temperature grade) updated accordingly). Small text changes. WLCSP package added (see Figure 3: WLCSP connections (top view, marking side, with balls on the underside) and Section 7: Package mechanical data). M24256-BF part number added (VCC = 1.7 V to 5.5 V voltage range added, see Table 10, Table 15, Table 16 and Table 24). ICC1 test conditions modified in Table 13: DC characteristics (voltage range W), Table 14: DC characteristics (voltage range R) and Table 15: DC characteristics (voltage range F). M24512-DR part number and Identification page feature added. Command replaced by instruction in the whole document. UFDFPN8 added. Figure 6 updated. Section 2.6.2: Power-up conditions and Section 2.6.3: Device reset updated. tCLQX and tCLQV updated in Table 16, Note 5 and Note 8 added. tCLQX and tCLQV updated in Table 17, Note 6 and Note 9 added. Section 8: Part numbering updated. Reference to the SURE program removed in Section 5: Maximum rating. Previous 1 MHz M24512-HR and M24512-BHR devices replaced by new M24512-R and M24256-BR (process letter K).
14-Dec-2007
9
27-Mar-2008
10
22-Apr-2008
11
22-Dec-2008
12
21-Jan-2009
13
05-Jun-2009
14
40/42
Doc ID 6757 Rev 21
M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 26.
Date 16-Jun-2009 20-Aug-2009
Revision history
Document revision history (continued)
Revision 15 16 Changes Part numbers updated in cover page header. IOL added to Table 8: Operating conditions (voltage range W). Note 1and ICC modified in Table 13: DC characteristics (voltage range W); Note and ICC modified in Table 14: DC characteristics (voltage range R); Datasheet split to leave only devices with 256 Kbit capacity. M24256-DR part number added (see Table 25: Available M24256-DR products (package, voltage range, temperature grade). Figure 4: Device select code and Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) updated. VIO max modified in Table 7: Absolute maximum ratings. VIH modified in Table 13: DC characteristics (voltage range W), Table 14: DC characteristics (voltage range R) and Table 15: DC characteristics (voltage range F). In Table 16: 400 kHz AC characteristics and Table 17: 1 MHz AC characteristics: - tDL1DL2 changed to tQL1QL2 - tCHDX changed to tCHDL - tXH1XH2 and tXL1XL2 values removed - Notes modified Figure 13: AC waveforms modified. Section 3.9: Identification Page Write (M24256-DR only) corrected.Section 3.17: Read Identification Page clarified. UFDFPN8 package is now offered (see Section 7: Package mechanical data, Table 23: Ordering information scheme and Table 24: Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade). Revision number corrected at bottom of pages. Process description corrected in Table 23: Ordering information scheme.
13-Oct-2009
17
05-Nov-2009
18
10-Dec-2009
19
19-Jan-2010 04-Mar-2010
20 21
Doc ID 6757 Rev 21
41/42
M24256-BF, M24256-BR, M24256-BW, M24256-DR
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
(c) 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
42/42
Doc ID 6757 Rev 21

▲Up To Search▲

Price & Availability of M24256-BF

	To Download M24256-BF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .